The present invention relates generally to large scale integrated (LSI) chip designs, and more particularly to a method and system for testing the data access time of a macro module embedded therein.
Due to the extremely tight timing constraints of today's LSI system on chip (SOC), timing parameters of an embedded macro module are a critical synthesis parameter. Therefore, it is imperative that measurements of the timing parameters of these embedded macros are performed, accurately and adequately.
For example, random access memory (RAM) macro modules and the like which are embedded within such LSI chips are always surrounded by intervening circuitries including, for example, logic elements, and input/output (I/O) interface circuits. As a result, the embedded macro modules are not directly accessible from the input and output terminals of an integrated circuit chip. The intervening circuitry causes on-chip time delays associated with input and output signals. These delays prohibit accurate timing measurement between, for example, macro-enable signals and test signals during a test, since the associated time delay caused by the intervening circuitries for a given signal is unknown.
While various conventional methods and devices exist, the strategy of timing measurements is to compensate for the on-chip time delays. For example, these test methods and devices usually include complicated elements that bypass the intervening circuitry so that the macro module is directly accessible from primary inputs ts. However, this not only complicates the circuit design, but also makes it hard to obtain an accurate timing measurement.
Therefore, desirable in the art of testing timing parameters of embedded macro modules is an improved method and system to accurately measure the timing parameters, without excessively complicating the circuit design.